Embedded FPGA Developments in 130nm and 28nm CMOS for Machine Learning in Particle Detector Readout
Date:
[indico page](https://indico.cern.ch/event/1348862/timetable/) Embedded field programmable gate array (eFPGA) technology enables embedding of reconfigurable logic within design of an application-specific integrated circuit (ASIC). It combines the dual benefit of FPGA’s reconfigurability and ASIC’s low power consumption. Specifically, eFPGAs can enable the implementation of ML algorithm on the front-end readout chip for collider detectors, helping to mitigate high data rates from future collider experiments. We designed, fabricated, and validated eFPGA on 130nm and 28nm CMOS technology nodes with an open-source framework, “FABulous”. A boosted decision tree (BDT) classifier was synthesized and configured on the 28nm chip to reject pileup tracks at-source using the simulated “Smart Pixel” dataset. We successfully demonstrated the proof-of-concept through perfect reproduction of the expected algorithm result on the eFPGA, and briefly discuss next steps for advancing the technology.
